In semiconductor processing, a reticle (sometimes referred to as a photomask) is used to form a pattern on a wafer, or more precisely, on a photoresist on the wafer. Typically, the reticle is used in an imaging system that projects an image of a pattern in the reticle onto a target region of the wafer. A reticle often has a “die array” with a small space between adjacent dice in the array. This space between the dice is referred to by various names including scribe lines, scribe lanes, kerfs, and streets. Typically, each die in the array has a pattern that is used to form one layer of an integrated circuit. As the overall circuit design usually has many layers, typically a different reticle is used for each layer. Thus, the pattern in one die on the reticle is transferred to the wafer to form one layer of the integrated circuit.
Just as the patterns in the die array can be transferred from the reticle to the wafer, patterns can be transferred from the reticle scribe line to a wafer scribe line. The patterns in the scribe lines are required for correct processing of the wafer. Herein, the term scribe line may be used to refer to either a scribe line of a reticle or a scribe line of a wafer. The scribe lines have been used for various purposes. For example, test and measurement structures may be formed in the wafer scribe lines by transferring patterns from the reticle scribe lines. As a particular example, a semiconductor test device or test circuit could be formed in the wafer scribe line. After using these test structures to test whether the circuit fabrication process was successful, the test structures are destroyed when the chips are removed from the wafer by, for example, cutting along the wafer scribe lines.
The reticle scribe lines can also be used for process control. For example, a pattern, such as alignment marks or inspection keys, can be transferred from the reticle scribe lines to the wafer scribe lines. The alignment marks can be used to verify that each new layer that is formed on the wafer is precisely aligned with the lower layer. The reticle scribe lines can also contain marks that are used during the manufacture of the reticle itself.
As lithography process technology moves to smaller and more closely spaced features, it becomes more difficult to print the design from the reticle onto the wafer due to resolution limits. A primary limitation is how closely features can be spaced due to optical limitations. This is so even if resolution enhancement techniques (RET) such as optical proximity correction (OPC), immersion scanning, and phase shift masks are employed.
Double patterning is a technique that has been considered to achieve more closely spaced features. In double patterning, two reticles are used to print split portions of an original pattern onto a hard mask that, in turn, is used to transfer the original pattern to the substrate. To print two patterns on the hard mask, the original pattern is split into two or more patterns where each has a narrowest pitch that is wider than the narrowest pitch in the original pattern. Each of the split patterns is printed to a separate reticle. First one reticle is exposed onto a photoresist above the hard mask. The photomask is removed and the pattern is transferred from the hard mask to the wafer. After transferring the first pattern from the photomask to the wafer, a new layer of photoresist is applied to the wafer and another photomask is added above the hard mask. Next, the second reticle is exposed onto the second photoresist. After transferring the second pattern to the hard mask, the second photomask is removed and the second pattern is transferred from the hard mask to the wafer, resulting in the combined pattern being transferred from the two reticles to the wafer.
However, for such a technique to be effective, the exposure of the two split patterns needs to be precisely aligned such that the original pattern is achieved. However, lithography techniques have limitations in how precisely the two patterns can be aligned.
Thus, improved techniques for forming devices, such as semiconductors, having narrow pitches are desired.
The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.